A technique for correction of parasitic capacitance on microwave f/sub t/ measurements of MESFET and HEMT devices
1991
A technique for determining the parasitic capacitance attributed to device layout geometry is described. This simple technique requires only on-wafer, cascade probe measurements on devices with varying gate widths. This technique will assist in the optimization of device layout design and in improving modeling performance for microwave and millimeter-wave applications. >
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