COOL substrate for 2.5D assembly

System integration with high data transmission often demands packaging solution having fine line routing capability in order to deliver the desired performances with better power and signal integrity. However, while wafer fabrication is advancing at a relentless pace, IC substrate technology has not been able to catch up device's fine feature needs at reasonable cost. This is due mainly to resin materials' poor mechanical stability and equipment limitations of current manufacturing infrastructure. As such, inorganic interposer such as silicon and glass interposers have been investigated intensively with their excellent material properties such as low CTE, high modulus and through-via processing capability. However, even fine feature interposer can meet devices' interconnect needs, most of 2.5D architectures adopt chip-first assembly methodology, which suffers high manufacturing cost due to high yield loss and thus limits their applications only in a very narrow area. This paper will describe an innovative chip-last 2.5D assembly using an integrated substrate namely, Carrier-on-Organic-Laminate (COOL) substrate to address fine pitch interconnection and manufacturing infrastructure issues. Structurally, COOL substrate has an interposer embedded in a build-up laminate and supported by a stiffener. The interposer can be chosen from ceramic, organic, glass, or silicon-based chip carrier depending on device routing density requirements and cost constraint. As interposer/laminate is interconnected by micro-via plating process (a low temperature process and devoid of solder reflow), thermal induced stress and interposer warpage problems can be largely resolved. As such, unlike most conventional 2.5D approaches where chip(s) are attached on an interposer before being assembled on HDI substrate by solder, COOL substrate allows most difficult chip-attachment process as the very last assembly step. In other words, COOL substrate simplifies the entire 2.5D assembly by enabling only one high temperature solder reflow process (e.g., micro-bump thermal compression) on a known good interposer/substrate. From the electrical performance viewpoint, COOL substrate minimizes the large power losses caused by the parasitic resistances and inductance introduced by conventional HDI substrate's plated through holes in core layer. Stiffener in COOL substrate can provide mechanical support and warpage management for the entire board. While the interposer maintains flatness in the central region, the stiffener control the warpage from periphery and this low warp feature allows copper pillar bumps be adopted in flip chip assembly. The paper will illustrate how the COOL substrate can be adapted for conventional flip chip assembly without incurring expensive new equipment and new tooling. Other benefits such as better thermal dissipation pathway and supporting Package-on-Package assembly solution will be described as well.