Electrical characterisation and predictive simulation of defects induced by keV Si+ implantation in n-type Si

In this work, we focused on the analysis of implantation-induced defects, mainly small interstitial clusters (ICs) and {311} defects introduced in n-type Si after ion implantation using deep level transient spectroscopy (DLTS). Silicon ions (at 160 keV or 190 keV) of fluences ranging from (0.1–8.0) × 1013 cm−2 have been implanted into n-type Si and annealed at temperatures between 500 °C and 800 °C specifically to create small ICs or {311}s rod-like defects. In samples dominated by small ICs, DLTS spectra show prominent deep levels at Ec − 0.24 eV and Ec − 0.54 eV. After increasing the fluence and temperature, i.e., reducing the number of small ICs and forming {311} defects, the peak Ec − 0.54 eV is still dominant while other electron traps Ec − 0.26 eV and Ec − 0.46 eV are introduced. There were no observable deep levels in reference, non-implanted samples. The identity and origin of all these traps are interpreted in conjunction with recently developed predictive defect simulation models.