Random Pattern Testability Enhancement by Circuit Rewiring

Generally, there exist random-pattern resistant faults that result in the poor fault coverage in Build-In Self-Testing (BIST) scheme. In this paper, we propose a method to enhance the random pattern testability by a circuit restructuring technique, called circuit rewiring. The basic idea of rewiring is to replace a wire by another wire with the circuit functionality remaining unchanged. For two types of rewiring, fanin rewiring and fanout rewiring, we first analyze the testability change for each type of wire replacement. Based on the analysis, an efficient algorithm is given to enhance circuit testability. For a poor observability node, we try to increase its observability by adding an additional fanout to the node and removing an alternative wire whose source node has relatively good observability. The technique does not introduce any hardware overhead and performance degradation since a wire addition is followed immediately by another wire removal. Thus, it is basically cost-free when compared to other testability enhancement techniques.