8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range

System-on-chip (SoC) processor cores experience high-frequency supply voltage (V DD ) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim to reduce the effects of V DD droops by sensing the V DD variation with an on-die monitor and adjusting the clock frequency (F CLK ) [1-2] or by directly modulating the phase-locked loop (PLL) clock output with changes in the core V DD to implicitly adapt F CLK [3]. The adaptive response time and complex analog circuits limit the benefits of these techniques for a wide range of F CLK and V DD operating conditions. The adaptive clock distribution (ACD) [4-5] exploits the path clock-data delay compensation during a V DD droop to enable a sufficient response time to proactively adapt F CLK . Although the ACD mitigates the impact of V DD droops on performance and energy efficiency, the previous designs require extensive post-silicon tester calibration of the dynamic variation monitor (DVM) to accurately detect the onset of the V DD droop. Since SoC cores operate across a wide range of F CLK , V DD , temperature, and process conditions, the DVM requires a unique calibration for each operating point, thus resulting in prohibitively expensive test time for high-volume products. This paper describes an ACD design in a 16nm [6] test chip with an auto-calibration circuit to enable in-field, low-latency tuning of the DVM across a wide range of operating conditions to maximize the ACD benefits, while eliminating the costly overhead from tester calibration.