Processor system in parallel processing design and method of controlling

Processor in parallel processing type comprising: N execution units (103-110) for concurrent processing of instructions, where N is an integer; an instruction supply means (102) for supplying commands through the N execution units (103-110) are to be simultaneously processed; and a trap controller (133) for controlling the N execution units (103-110) in such a manner that when M commands from the command supply device (102) the N execution units (103-110) are fed simultaneously, wherein M is an integer and N ≥ M, and an exception condition during processing of at least one of the M commands is caused in one cycle, the processing of all M commands that the N execution units (103-110) are fed simultaneously, be aborted in this cycle, not in set among the M commands that cycle a trap address of an instruction by which the exception condition is caused.