Evaluation of POD and APOD multicarrier SPWM techniques for three-phase seven-level diode clamped multilevel inverter fed induction motor drive using FPGA

Multilevel inverters have drawn tremendous interest in high power high voltage applications due to their merits such as reduced voltage stress on switches, lower EMI problems and reduction in THD. The MLI technology is also advantageous in improving output waveforms due to the higher number of levels in the waveform of output voltage along with a reduced input filter size which is useful for grid connected applications. This paper focuses on implementation of three-phase diode clamped multilevel inverter fed induction motor drive using various multicarrier-based sinusoidal pulse width modulation techniques. The performance analysis of the inverter is carried out using phase opposition disposition (POD) and alternate phase opposition disposition (APOD) techniques. In addition to this, the comparison of the modulation methods is also analysed. Simulation is performed using MATLAB/Simulink. The POD and APOD carrier-based sinusoidal pulse width modulation techniques for three-phase seven-level diode clamped multilevel inverter are implemented on VPE Spartan 3A DSP board using Xilinx field programmable gate array (FPGA) and the experimental results are presented to validate the effectiveness of the operation of the seven-level diode clamped multilevel inverter using PWM strategies.