Simulation study on influence of interface trap position in Sii-xGex Gate-All-Around (GAA) field-effect transistor

In this paper, performance degradation of Si 1−x Ge x gate-all-around (GAA) Field-Effect Transistor (FET) depending on interface trap position was investigated through TCAD simulations. Interface traps were located at three different points along the channel. Parameters such as hole mobility and energy band were analyzed to understand the effects of partially generated interface traps by unstable GeO x .