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A Sub-nanoampere Two-stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Batteryless Sensor Nodes
A Sub-nanoampere Two-stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Batteryless Sensor Nodes
2010
M. Ugajin
T. Simamura
S. Mutoh
Mitsuru Harada
Keywords:
CMOS
Power management
Computer science
Electronic engineering
Electrical engineering
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