Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors

Degradation in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (S.S.) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in S.S. values which appears in hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.