Layout Geometry Impact on DDSCR Devices for High Voltage ESD Protection

DDSCR devices with finger-type, snake-type and track-type layout are studied and fabricated in $0.5\mu \mathrm{m}$ 18V CMOS process. The finger-type DDSCR achieves the highest failure current about 13.06A, which is also the device that occupies the smallest chip area in three layout styles. In view of the efficient discharge capability (It/area), the finger-type structure provides more than 50% and 66% current handling capability per area higher than the snake-type and track-type, respectively. Due to its better area efficiency, the finger-type structure should be a promising layout of the DDSCR in the input and output ports ESD protection applications.