A novel high-density 5F/sup 2/ NAND STI cell technology suitable for 256 Mbit and 1 Gbit flash memories

This paper describes a novel high density 5F/sup 2/ (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31 /spl mu/m/sup 2/ has been obtained for the 0.25 um design rule. To minimize the cell size, a floating gate is isolated with a shallow trench isolation (STI) and a slit formation by a novel SiN spacer process, which has made it possible to realize a 0.55 /spl mu/m-pitch isolation at a 0.25 /spl mu/m design rule. Another structural feature integral to the cell and its small size is the borderless bit-line and source-line contacts which are self-aligned with the select-gate. The proposed NAND cell with the gate length of 0.2 /spl mu/m and the isolation space of 0.25 /spl mu/m shows a normal operation as a transistor without any punch-through. Therefore, this 5F/sup 2/ NAND STI cell technology is essential to realize a low cost flash memories of 256 Mbit and 1 Gbit for mass-storage applications.