A method for forming interconnects for three-dimensional integrated circuit

A method for forming interconnects for three-dimensional integrated circuits comprising: applying a metal layer on a first substrate, attaching a first side of a Kapselungskomponente on the metal layer, wherein the Kapselungskomponente comprises a plurality of vias. The method further comprising: filling the plurality of vias with a metal material by an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, mounting a second carrier to a second side of Kapselungskomponente, detachment of the first carrier from the Kapselungskomponente, forming a photoresist layer on the metal layer, patterning the photoresist layer and stripping exposed portions of the metal layer.