Low power performance SRAM cell design

Abstract The Static Random Access Memory (SRAM) is shown vital in high performance portable VLSI Chips due to their performance and storage density. This paper presents the evaluating point by point recreation derive for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture. The adiabatic low power technique is implements to enrich the configuration of 6T-SRAM cell. The approach and application of this adiabatic driver the more loss of energy dissipation to the ground (0 V) with ‘1’ to‘0’ transition is decreased to a larger degree in the memory cell. This method gives a lower degree of power reduction results compared with the standard adiabatic 6T-SRAM cell.