Impact of Bottom Interfacial Layer on the Threshold Voltage and Device Reliability of Fluorine Incorporated PMOSFETS with High-K/Metal Gate

The effect of F implantation combined with high quality bottom interfacial layer has been investigated in terms of threshold voltage reduction and improvement of device performance of TaCN/AlN/HfSiOx gate stacks for PMOS application. Threshold voltage becomes more positive as AlN, F implantation, and thermally grown interfacial layer steps are added. It is found that F accumulates near the interface with the Si substrate and the observed V th shift has been attributed to the passivation of positively charged defects in the dielectric stack and additional negative charge associated with F atoms. Thermally grown interfacial layer combined with F implantation resulted in excellent device parameters and reliability as well as lower PMOS Vth due to inherently lower defect density and defect passivation effect by F atoms.