Method for using fpga to realize 32-bit addressing and accessing of sv data

Provided is a method for using an FPGA to realize 32-bit addressing and accessing of sample value (SV) data, for a device in an intelligent transformer substation to process digital SV data. The method comprises the following steps: an FPGA receives a raw packet of SV data based on the IEEE802.3 standard, analyzes the data structure of an Ethernet frame, utilizes the characteristics of the ASN.1 encoding rule to reorganize the SV data of a network byte order according to the Ethernet frame characteristics of the SV data, and converts the reorganized SV data into data capable of being directly accessed by a pure 32-bit addressing processor, thus greatly improving SV decoding efficiency. When a pure 32-bit addressing processor splits and reintegrates via software the SV data of a network byte order, the efficiency is dramatically reduced. The present invention solves the problem, and improves the decoding efficiency by 5-10 times.