Resin coated copper capacitive (RC3) nanocomposites for system in a package (SiP): Development of 3-8-3 structure

Embedded passives account for a very large part of today's electronic assemblies. This is particularly true for products such as cellular phones, camcorders, computers and several critical defense devices. Market pressures for new products with more features, smaller size and lower cost demand smaller, compact, simpler substrates. An obvious strategy is to reduce the number of surface mounted passives by embedding them in the substrate. In addition, current interconnect technology to accommodate surface mounted passives imposes certain limits on board design which constrain the overall system speed. Embedding passives is one way to minimize the functional footprint while at the same time improving performance. This paper discusses thin film technology based on resin coated copper capacitive (RC3) nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of RC3 nanocomposite thin films ranging from 8 microns to 50 microns thick were processed on Cu substrates by liquid coating. Multilayer embedded capacitors resulted in high capacitance 16–28 nF. The fabricated test vehicle also included two embedded resistor layers with resistance in the range of 15 ohms to 100 kohms. To enable high performance devices, an embedded resistor must meet certain tolerances. The embedded resistors can be laser trimmed to a tolerance of ≪5%, which is usually acceptable for most applications. We have an extended embedded passives solution that has been demonstrated both through its high wireability designs and package performance to be perfectly suited for the system in package (SiP) applications. As a case study, we have designed and fabricated eight layer high density internal passive core and subsequently applied fine geometry 3 buildup layers to form a 3-8-3 structure. The passive core technology is capable of providing up to 6 layers of embedded capacitance and could be extended further. This effort is an integrated approach centering on three interrelated fronts: (1) materials development and characterization; (2) fabrication, and (3) integration at the device level.