Comparative analysis of LUT design In FPGA

In FPGA, Look Up Tables (LUT) and routing multiplexer are configured using SRAMs. The Look Up Table also a multiplexer that implements a truth table each input combination generates a certain output. The inputs of the Look Up Table is connected to the SRAM cells. There are many ways to design a logic block; one approach is to use multiplexer. This paper represents the simulation of different multiplexer structures for Look Up Table design.