Double dipole lithography for 65-nm node and beyond: a technology readiness review

Double Dipole Lithography (DDL) has been demonstrated to be capable of imaging complex 2D patterns for full-chip application. Due to inherently high aerial image contrast, we have found that there is strong potential for this technology to meet manufacturing line width roughness (LWR) and critical dimension uniformity (CDU) requirements for the 65nm node using ArF binary chrome masks or 6% attenuated phase shift mask (AttPSM). For patterning at k 1 less than 0.35, DDL is a Resolution Enhancement Technology (RET) that offers an acceptable process window without resorting to costly hard phase shift masks. To use DDL for printing actual IC device patterns, the original design data must be converted into “vertical (V)” and “horizontal (H)” masks for the respective X and Y dipole exposures. An improved model-based DDL mask data processing steps has been demonstrated that it is possible to convert complex logic and memory data to X-Y dipole exposure compatible layout. Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of chrome in open field areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for most poly gate masks using a positive resist process. In this work, we report an improved model based DDL layout conversion methodology for full-chip application. A new generation of DDL technology reticle set was developed to verify the performance. Background light shielding is a critical part of the DDL. We report an innovative shielding scheme to minimize the negative impact of stray light for the critical features during double exposures.