A real-time digital VCR encode/decode and MPEG2 decode LSI implemented on a dual-issue RISC processor

A real-time system LSI for Digital VCR (DVCR) encoding/decoding and MPEG2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware for variable length coding/decoding and video-block loading. The DRISC achieves 972MOPS and supports multiple standards with the block-level dedicated processing. The LSI size is 7.7×7.2mm 2 in a 0.25-µm process.