Multigate Ferroelectric Transistor Design Toward 3-nm Technology Node

2021 
An advanced gate-stack design of ferroelectric (FE) transistors has been proposed and investigated for logic compatible program/erase voltage, better scalability, and suppressed depolarization field. The ferroelectric-metal (FeM) FinFET (FeM-FinFET) and stacked nanosheets transistor (FeM-Nanosheet), which have an FE layer on top of the transistor's gate, could adjust the area ratio (AR) between the FE capacitor ( $A_{FE}$ ) and the MOS capacitor ( $A_{MOS}$ ) (AR = $A_{FE}$ / $A_{MOS}$ ) using the floating gate between them, thereby enhancing the electric field on the FE layer. In particular, the proposed FeM-Nanosheet could have the flexibility to lower the operating voltage and depolarization field by increasing the number of nanosheets to reduce the AR.
    • Correction
    • Source
    • Cite
    • Save
    • Machine Reading By IdeaReader
    11
    References
    0
    Citations
    NaN
    KQI
    []