A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique

This paper presents a novel disturb mitigation technique which achieves low-power and low-voltage SRAM. Our proposed technique consists of a floating bitline technique and a low-swing bitline driver (LSBD). We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed technique achieves 1.52-pJ/access active energy in a write cycle and 72.8-μW leakage power, which are 59.4% and 26.0% better than the conventional write-back technique.