Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM

Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest for its characteristics of scalability, nonvolatility, and small cell size. As the technology node is scaled down, however, the sensing margin (SM) and read disturbance margin (RDM) of the STT-RAM are degraded because of increased process variation, decreased supply voltage, and reduced critical switching current. In this brief, we propose a half-pulsewidth read disturbance (HPWRD) scheme that is capable of significantly improving the RDM by reducing the read disturbance time by half. Results from a Monte Carlo HSPICE simulation using the parameters of a 45-nm industry-compatible model show that the HPWRD scheme produces a three-order improvement in the RDM without sacrificing the SM, speed, or energy efficiency, at the cost of an increased area overhead of 4.12% for a subarray size of 128 $\times$ 16.