Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins

With the development of the Internet of things (IoT), sensors are being mounted on various objects. This trend has prompted demand for low-power, high-performance information processing on the edge side. Here, an Ising model architecture that can efficiently solve optimization problems would be an efficient processing solution for edges. In this study, we implemented a 512-spin fully connected Ising model on an LSI chip fabricated in a 28-nm CMOS process. The fully connected Ising model was implemented in the chip by using pseudo-annealing (PA), which is easier to implement than simulated annealing (SA). In addition, we devised a multi-spin-thread structure, concurrent update structure, and a folded interaction placement for accuracy, speed, and compactness. Because eight spin threads are implemented, the calculation throughput could be increased by a factor of eight in comparison with a single spin-thread implementation. Moreover, as a measure of solution accuracy, the average route length of a 22-city traveling salesman problem was reduced by 19% and the standard deviation (SD) was reduced by 46%. Likewise, the average cut value of a 512-node max-cut problem was increased by 1.6% and SD was decreased by 60%. The concurrent update almost doubled the calculation speed in comparison with the case of no concurrent update. In addition, the circuit area was reduced by about 38% as a result of the folded interaction placement. The time required to obtain a solution was 128 ms. The chip at annealing processing (main processing) had a power consumption of 12 mW at 1 MHz.