Research of Failure Models for a 700 V VDMOSFET

The failure models of 700 V VDMOSFET have been established according to the test results. The maximum theoretical breakdown voltage of 520 V and the simulation of the failure models are in agreement with the failure analysis and the test result. It's believed that the failure is induced by the large space between the junctions due to the inappropriate gate-pad area layout design. Two schemes are given to construct a large junction under the gate-pad to solve the failure problem in this paper. The first scheme is that the total gate-pad area is covered by the GR mask usually used to form the deep field limiting rings (FLRs) to support high voltage. In the second scheme, the GR mask is instead by the AA mask resulting in a shallow junction with a modified length of polysilicon-gate-bus. The validity of two schemes has been proved by the simulation. Only the first scheme has been implemented because of the second tape-out cost, and the final test breakdown voltage is about 710 V almost satisfying the design target.