A methodology for dynamic power consumption estimation using VHDL descriptions

Power consumption became an important feature to be considered in system implementations. This work presents a methodology for dynamic power consumption estimation using hardware descriptions written in VHDL; a library with information for transitions and power consumption for all components of the target library is created. A case study for the KASUMI cryptographic algorithm is reported. This algorithm was chosen to compose the 3rd Generation Partnership Project (3GPP) security functions for mobile systems. Restrictions imposed by the 3GPP to the hardware implementation of the KASUMI cryptographic algorithm were analyzed and satisfied; our dynamic power consumption estimation methodology is used. Only CMOS technologies are discussed in this paper.