A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 $\mu \text{m}^{2}$ 6T SRAM bitcell is designed for high density (HD), and 0.049 $\mu \text{m}^{2}$ for high performance (HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ( $V_{\mathrm{ MIN}}$ ) and assist overheads. The dual-transient wordline scheme is proposed to improve the $V_{\mathrm{ MIN}}$ by 47.5 mV for the 128 Mb 6T-HP SRAM. The suppressed bitline scheme with negative bitline improves the $V_{\mathrm{ MIN}}$ by 135 mV for the 128 Mb 6T-HD SRAM. The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications.