Implementation of Low-Power 6T SRAM Cell Using MTCMOS Technique

Electronics industry in present-day scenario is facing the major problem of standby leakage current in most of the electronic devices. As the speed of processor is increasing, the demand for high-speed cache memory is ever increasing. SRAM being mainly used for cache memory design, several low-power techniques are being used to reduce its leakage current. Full CMOS 6T SRAM cell is the most preferred choice for most of the digital circuits. This paper implements 6T CMOS SRAM cell using MTCMOS technique and simulation results show significant reduction in leakage during standby mode. The simulations are done on Cadence Virtuoso Tool using 45 nm technology.