Efficient Filter Implementation Using Cutset Retiming and Pipelining Approaches

A filter is an important component for analysing a signal. Most of the applications requires the process to be done as fast as possible to obtain the required result. The speed and efficiency of the filters depend upon the propagation delays across the data path. In conventional filtering techniques, data dependency requirement which has large propagation delay which also leads to undesirable pipelining. This efficient implementation is achieved using applying retiming and pipelining schemes in FIR filter with different lengths. Retiming is an approach which is involving in changing the location of delay elements in filters to reduce the critical path. The retiming techniques with splitting and merging of nodes will achieve a minimum clock period and reduce the unwanted pipelining. Suitable pipelining technique is also utilized along with the retiming technique to enhance the speed of a filter. The techniques implemented on design of FIR filters are compared according to their performance and the simulation results and design summary reports are obtained using Model Sim Altera-6.6d (Quartus II 11.0 sp1) and Xilinx ISE14.7 with Spartan6 family XC7A100T device.