Transistor Subthreshold Swing Lowered by 2-D Heterostructures

Steep-slope transistors are required for low-power electronic applications. However, the strategy to lower the subthreshold swing (SS) remains elusive. Here, we present a method based on altering capacitance constitution to lower the SS of 2-D transistors close to thermionic limit (60 mV/dec). By inducing other 2-D materials with opposite carrier type into the channel, the extra junction capacitance is in series with the channel capacitance, leading to lower semiconductor capacitance and lower SS. The electrical performance of conventional 2-D transistor with pure WSe2 channel and WSe2-BP-MoS2 heterojunction channel is studied and compared. The 2-D transistor with pure WSe2 channel shows SS ~ 110 mV/dec. After forming WSe2-BP-MoS2 heterojunction channel, the SS reduces to ~62 mV/dec and maintains over three orders of magnitude. To reveal the mechanism, a compact model based on Landauer formula has been established. The simulation results indicate that lower SS has strong relation with the reduction of semiconductor capacitance. The proposed structure provides a new way to develop steep-slope transistors.