Architecture of a new ASIC data communication circuit intended for the ISO levels 3, 4, 5: network, transport and session

The functional specification and the architecture of the MC3 chip are described. Specific advanced aspects of this work concern at first the main target: a novel application-specific integrated circuit (ASIC) data communication circuit intended for the high-level ISO protocols network, transport, and session. Secondly, they concern the functional requirements of the target circuit: it must run each announced level or a subset of the 3 levels; with each hypothesis are given an upper bound for the number of authorized connections, and a lower bound for the corresponding throughput. Emphasis is placed on the definition of the MC3 chip architecture, its external interface and the embedded systems architecture in which the chip will operate. It is also shown how the validation of the whole defined architecture is carried out: by implementing a high-level simulation on a multi-Transputer-based machine and by logical simulation. >