Development of VLSI of entropy coding for digital video

With the recent development of the digital electrical communication network and the advent of low-cost large-capacity digital storage media, an effort is made toward the digitization of the TV signal. Along with this, the image coding technique is becoming more important, where the research emphasis is shifting from the low bitrate pseudodynamic image representation, to high-resolution, high-quality images. Among various image coding methods, the feature of the entropy coding based on Huffman coding [1–3] is that a large amount of image data can be compressed efficiently by combining discrete-cosine transform (DCT) and the motion-compensated interframe coding, and is used presently as the indispensable element of the algorithm. To apply the method to the future digital dynamic image with a high image quality requirement and to realize the real-time processing, it is necessary to develop a fast processing architecture for the Huffman coding, together with its VLSI implementation. With this as background, this paper describes the fast processing architecture for the Huffman coding developed by the authors, together with its VLSI implementation.