A low-power two-stage harmonic rejection quadrature mixer employing bias-current reuse

A bias-sharing two-stage harmonic rejection mixer that provides quadrature baseband outputs is demonstrated. The devices that bias the RF transconductors in a one-stage harmonic-rejection downconverter are configured to provide a second-stage of harmonic rejection for reducing the impact of gain coefficient errors, without requiring additional bias current. Clock retiming is used to desensitize the design to clock phase errors. The design is implemented in a 130nm CMOS process, and demonstrates a gain of 35.8 dB, an in-band output 1dB compression of −6 dBVp, a DSB NF of 11.5 dB, and an analog power dissipation of 14 mW from a 1.2 V supply. Harmonic rejection in excess of 60 dB is measured without calibration. Operation using a clock frequency in the range from 800 MHz to 2 GHz is verified. Mechanisms relating to bias-sharing that can potentially degrade performance including flicker noise and even-order harmonic response are identified. Circuit techniques for mitigating these issues that exploit orthogonal phasing of RF and baseband signals are described.