Energy Efficient Electrical Intra-Chip-Stack Communication

Through-silicon via (TSV) based 3D chip stacks provide many resources for compact and fast inter chip communication within a chip stack. They allow the design of highly integrated, heterogeneous, and compact systems with reduced overall power consumption, but very limited heat dissipation capability. This chapter presents a holistic packet-in packet-out point-to-point link architecture suitable for constructing a 3D network-on-chip (NoC) for connecting several processing elements within a Globally Asynchronous Locally Synchronous (GALS) design in a chip stack. This architecture has been implemented for long distance on-chip communication and for intra-chip-stack TSV based communication. After presenting a TSV behavioral description, models, hardware results, and a method for equivalent circuit parameter extraction, an energy efficient, capacitive coupling TSV transceiver is presented.