Design of a Custom Packet Switching Engine for Network Applications

This paper addresses the design of an application-specific processor with emphasis on packet processing applications. In this domain, demands for increasing the performance and the ongoing development of network protocols both call for flexible and performance-optimized engines. We present a flexible engine that is optimized for packet switching operations. The architecture and instruction set of our packet switching engine is designed based on a quantitative study of packet switching applications. Based on the extracted guidelines, architecture of our proposed communication micro engine (CME) is designed and verified with functional simulation. Comparative results show that at least 2-3 times performance gain can be achieved by using CME. A single CME core operates at 400Mbps, while it has an area of 1.6 mm2 and consumes 60mW of power when synthesized in 0.13μm CMOS technology.