Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effec- tive sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping cir- cuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5- m CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm dissipating 550 W while the digital-to-analog converter occupies 0.28 mm dissipating 600 W.