Determination of three-dimensional deep level defect distribution by capacitance-voltage transient technique (CVTT)

In this work we present the application of the CVTT technique to obtain three-dimensional distributions of deep level defects in boron ion implanted silicon wafers which were rapid thermal annealed just after the implantation process. The surface temperature is not homogeneous along the wafer during the RTA and, in consequence, the resulting damage varies from one point to another. Our results show the existence of a strong dispersion in the damage profiles. Moreover, the total amount of damage as well as its preferential location in the bulk vary with temperature showing a clear tendence. As temperature increases, the height and the depth of the damage peaks decrease, and the total amount of the damage increases. The fact that the deep level damage is non homogeneous over the wafer is very important because of its impact on the performance and yield of the electronic devices which will be later fabricated.