A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications

A very large scale integration (VLSI) implementation of an integrated adaptive beamforming processor and quadrature amplitude modulation (QAM) demodulator which will be incorporated into a frequency-hopped spread spectrum portable receiver for 2.4-GHz industrial, scientific, and medical (ISM) band applications is presented. The chip performs coherent QAM demodulation of variable constellation size and complete adaptive beamforming processing including four-channel adaptive beamforming combining, a fully programmable training processor, a readable/writable system control processor, an acquisition state machine, and a microcontroller interface. Interleaving area intensive blocks such as the 49-tap square-root Nyquist filters and 12/spl times/12 b multipliers is employed to reduce chip area. This chip can operate as a stand-alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for high bit rate indoor wireless applications. The core area of the chip is 6.22 mm/spl times/4.58 mm in 0.8-/spl mu/m CMOS technology, and the power dissipation is 610 mW at 5 V and a 5 MBaud symbol rate. In a 2.2-dB signal-to-interference-and-noise ratio environment, the receiver chip achieves a link quality of 32.6 dB SNR by performing digital adaptive beamforming to null out interferers.