Design and implementation of finite state machine decoders for phase disposition pulse width modulation of modular multilevel converters

It is well known that level shifted phase disposition pulse width modulation (PD-PWM) achieves the best possible three-phase line-to-line output voltage spectrum for multilevel converters. However the strategy does require post modulation signal decoding to optimally select between redundant switched states and to achieve an even distribution of commutation events across all switching devices. For modular multilevel converters (MMCs), PD-PWM involves firstly scheduling the individual module switching events of both arms as an integrated process to achieve optimal harmonic performance, and then selecting between redundant states to balance the individual module capacitor voltages, and to also minimise the phase leg high frequency circulating currents. This paper discusses the design and implementation of finite state machine PD-PWM post modulator decoders for MMCs to achieve these objectives. The proposed approach has been verified in simulation and then with experimental confirmation using a two module per arm MMC.