Technique for reducing topography dependent irregularities during the patterning of a dielectric material in a contact plane lying close transistors

In a double-stress layers technology, the surface conditions are improved after the patterning of a first stress-inducing layer by an etch sequence is designed for a substantially complete removal of an etch stop material in a suitable way, which material is used for patterning the second stress-inducing dielectric material, while in other cases, the etch stop material is selectively formed after the patterning of the first stress-inducing dielectric material. Thus, the double-stress layers technology can be efficiently for semiconductor devices of the 45 nm technology and used below.