Panel discussions: “Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?”

Moore's Law, doubling the number of transistors in a chip every two years, has so far been contributed to the evolution of computer systems, e.g., employing large on-chip caches, increasing DRAM (or main memory) capacity, introducing manycore accelerations, etc. The growth of such hardware implementation makes a lot of optimization opportunities available to software developers. Unfortunately, we cannot expect transistor shrinking anymore, i.e., the end of Moore's Law will come. On the other hand, our society strongly requires sustainable computing efficiency for the next generation ICT applications such as AI, IoT, Big-Data, etc. To satisfy such requirements, we have to rethink computer system designs from the bottom. The goal of this panel is to discuss and explore the future direction of computer system architectures by focusing on especially high-performance, low-power computing such as data-centers and supercomputers. We first try to share the knowledge, experience, and opinions of our excellent panelists and then discuss the technical challenges to overcome the scaling limits for obtaining sustainable power-performance improvements.