Using PARBIT to Implement Partial Run-Time Reconfigurable Systems

Field Programmable Gate Arrays (FPGAs) can be used to implement partial run-time reconfigurable (RTR) systems. A tool called PARBIT has been developed that transforms FPGA configuration bitstreams into partial bitstreams. With this tool it is possible to define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device. This paper presents PARBIT, the methodology used to design the partial RTR system, and three application examples.