Twin register architecture for an AI processor

A twin register architecture has been developed to improve the backtracking speed of Prolog programs. The twin register architecture is intended to realize a virtual infinite register set. The features of the architecture are: (1) only a small amount of hardware is needed, including a pair of register files, and (2) data transfer between the register and the memory is automatically executed. A register saving/restoring operation and the Prolog instruction are executed in parallel to reduce the overhead of memory accesses. The twin register architecture has been implemented in the IP704 AI processor to determine its effectiveness. Experimental results have shown that the execution time of the 8-Queen program is reduced by 15% in the case of the twin register architecture as compared with that for the ordinary architecture, in which saving/restoring are done by software. Also, the architecture is useful for register saving/restoring of the CALL/RETURN procedure in general procedural programs. >