A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN

This paper introduces a fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN. The 0.13 mum CMOS radio SoC, which integrates two dual-band (2.4 GHz and 5 GHz) RF transceivers, analog baseband filters, data converters, digital physical layer, media access controller, and a PCI Express interface, provides a low-cost low-power small-form-factor WLAN solution. The MIMO radio comprises two identical dual-band transceivers that share a common frequency synthesizer capable of operating in both integer-N and fractional-N modes. In 2.4 GHz mode, the transceiver uses a direct-conversion architecture with a 3.2 GHz fractional-N frequency synthesizer. Direct conversion is used primarily because of its simplicity and the area reduction it offers by eliminating the need for an IF path. A 3.2 GHz synthesizer frequency is used to avoid VCO pulling. The 3.2 GHz synthesizer output f vco is divided by two and then mixed with the original 3.2 GHz f vco to generate a 4.8 GHz frequency. This 4.8 GHz signal at twice the RF frequency is distributed to both transceivers. Within each transceiver, the 4.8 GHz signal is divided by two to generate the 2.4 GHz in-phase and quadrature LO signals. In the 5 GHz mode, the transceiver uses a sliding-IF dual-conversion architecture, in which the RF and IF LO signals are centered at 2/3 fRF and 1/3 fRF, respectively. The frequency synthesizer, operating in integer-N mode, thus provides a 3.2 GHz RF LO signal that is buffered and distributed to both transceivers. Within each transceiver a resistively loaded divide-by-two circuit is used to generate the quadrature LO signals at 1/3 fRF. The channel center frequencies in the 5 GHz band allow integer-N operation of the synthesizer with a relatively high reference frequency, thus improving the phase noise.