The Demonstration of Carbon Nanotubes (CNTs) as Flip-Chip Connections in 3-D Integrated Circuits With an Ultralow Connection Resistance

In this brief, the high-quality carbon nanotubes (CNTs) is grown by a chemical vapor deposition (CVD) method, and it is used as an ultrafine flip-chip interconnection material in the proposed 3-D integrated circuit (3DIC) system. We show a patterned growth of multiwalled CNTs on the substrate with prestructured bond pads including a complete metallization system for an electrical characterization. We succeeded in achieving reliable flip-chip connections between CNT-covered contact pads and metal pads during the room temperature bonding process. The goal is a reversible electrical and mechanical chip assembly with CNT bumps. Based on the current–voltage ( ${I}$ – ${V}$ ) measurements, the resistivity ( $\rho $ ) of the grown CNTs is found to be close to $\sim 10^{-{6}}\,\,{\sf \Omega }\text{m}$ . With the proposed 3DIC process flow, the vertically electrical connection between two different Si substrates is demonstrated successfully. The connection resistance in the full 3-D system is very promising ( $\sim 2.43~{\sf \Omega }$ ), compared with other’s work ( $\sim 12~{\sf \Omega }$ ). The different bonding materials (In versus Sn) and bonding times are also investigated systemically and further optimized. This brief provides a useful solution for the future electrical connection in the high-performance and high-dense 3-D integrated devices.