An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times

In this paper, an SRAM cell based on Dynamic threshold voltage MOSFET technique is analyzed for its performance in sub-threshold region. The cell utilizes a total number of 8 transistors with transmission gate based access transistors. Simulations are done on Cadence Virtuoso tool using 45nm GPDK in sub-threshold voltage regime. The proposed cell when compared with the conventional 6T SRAM cell shows 80% reduction in read access time, 63.95% reduction in write ‘1’ access time and 22.7% reduction in write ‘0’ access time. The proposed cell also shows 360% increase in Write static noise margin (WSNM). However, the power consumption is seen to increase by 400% during read operation, by 221.4% during write ‘0’ operation and by 458.4% during write ‘1’ operation.