Memory device with row decoder

Memory device having a word decoder, which includes word decoder: a word decode circuit (60) having an output to provide a set signal (SS3) in response to a predecoded row address signal (SS1, SS2); and a latch circuit (70A, 70B) coupled between the output of the word decode circuit (60) and one of word lines (WL) in a memory cell array, wherein the latch circuit (70A, 70B) comprises: a PMOS transistor (721, 711) and an NMOS transistor (722, 712) between first and second power source potentials (VDD, VSS) are connected in series; a first MOS transistor (73, 74A) connected to a PMOS transistor (721, 711) or the NMOS transistor (722, 712) is connected in parallel; and a second MOS transistor (73X, 74A) connected to the other of the PMOS transistor (721, 711) or the NMOS transistor (722, 712) connected in series, said second MOS transistor (73X, 74A) in such a manner is operated to an on / off state of the second MOS transistor is opposite to that of the first MOS Transistos, wherein a selection signal (WMSEL, ...