A group-commit mechanism for ROB-based processors implementing the X86 ISA

We introduce an alternative instruction commitment mechanism for a Reorder Buffer (ROB)-based out-of-order processor that commits a group of consecutive instructions atomically to support a larger instruction window. The proposed mechanism makes conservative use of the ROB, by only setting up entries for the instructions that perform the latest update to a register from that group. Further, the destination registers of instructions from a group that do not hold the most recent updates to architectural registers, can be released before the group containing these instructions is committed. The net result is an augmented ROB-based datapath, which increases the effective size of the ROB as well as the effective number of physical registers. The proposed design achieves an average performance gain of about 10% and 16% on the SPEC integer and floating point benchmarks, respectively, when compared to a traditional ROB-based design. The proposed design also achieves a performance gain of slightly over 5% when compared with an aggressive design that uses checkpoints and relatively complex hardware resources.