Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs

Longitudinal piezoresistance (pi) coefficients for n- and p-type double-gate (DG) FinFETs with sidewall channels along (110) surface and (110) channel direction are measured via wafer-bending experiments (51.4 and -37 X 10 -11 Pa -1 for n- and p-FinFETs, respectively) and are found to differ from bulk Si (110) (31.2 and -71.8 X 10 -11 Pa -1 for n- and p-Si, respectively). Compressive and tensile contact-etch-stop liners (CESLs) are fabricated on DG FinFETs and are found to induce higher channel stress than in planar MOSFETs, with 30% enhancement in the saturation current for the shortest channel-length devices in both n- and p-MOSFETs, whereas the long devices show little or no enhancement. The channel-length dependence of the enhancement suggests that stress coupling into the FinFET channels from the CESL occurs via the fin extensions and not through the gate.