A 16-bit 8-channel Sigma-Delta ADC for Harmonics Detection System in Power Network

This paper proposes a 16-bit 8-channel Simultaneously Sampled ADC for harmonics detection and analysis in power network. In each channel, a programmable gain amplifier (PGA) with protection of negative input is used to adjust signal amplitude, and a 3-order sigma-delta modulator is then used for quantization process. It utilizes chopping method to remove DC offset and low frequency noise of some amplifiers in key position and dynamic element matching (DEM) algorithm to maintain linearity of multi-bit feedback DAC in modulator. A prototype circuit has been designed in 0.18μm CMOS process. Post-layout simulation results demonstrate 98.3dB SFDR, 92.8dB DR and 14.9bit ENOB.